The present invention relates to a method of fabricating integrated circuits, and specifically, to a method of the manufacture of electrical conductive lines and, more particularly, to form buried bit line in a trench.
The large integration of semiconductor ICs has been accomplished by a reduction in individual device size. As the integration level of semiconductor devices, increases, each cell generally is reduced in size. To provide for such reduction in cell size, various techniques have been used to improve the performance of the device. For example, DRAM has been increased cell capacitance by increasing the effective area of a cell capacitor. To increase the capacitor""s effective area, stacked-capacitor and trench-capacitor structures, as well as combinations thereof, have been developed. With this reduction of device size, many challenges arise in the manufacture of the ICs. Each device requires interconnections for exchanging electrical signals from one device to another device. Specially, the high performance integrated circuits have multi-level connections separated by dielectric layers.
Many devices includes conductive lines for performing certain function, such as a bit line contact and a storage node contact must all be formed in a DRAM unit cell. Thus, design rules for minimizing area and ensuring adequate process margin are required. The bit line of the DRAM cell is usually comprised of a metal line, passing through an insulator layer and connecting to the active region. One method of minimizing the amount of area the bit line, of the DRAM device, occupies, is a buried bit line concept. In an effort to circumvent these technological problems, a buried bit line (BBL) cell in which a bit line is buried in the isolation region of a stacked cell, has been suggested. Dennison, in U.S. Pat. No. 5,250,457 has disclosed methods for fabricating a buried bit line.
Further, U.S. Pat. No. 5,840,591 to Park, et al., filed on Nov. 30, 1995, entitled xe2x80x9cMethod of manufacturing buried bit line DRAM cellxe2x80x9d. He disclosed a buried bit line DRAM cell which includes a buried bit line formed into a trench. A gate is formed to be orthogonal to the bit line on the substrate. A self-aligned bit line contact formed between a insulating layers for making contact between the drain and the buried bit line, and a self-aligned buried contact formed between the insulating layers for making contact between the source and a storage electrode.
A further method of fabricating a buried bit line includes a trench formed within the substrate by patterning an insulating layer and a substrate. Then a liner oxide is formed on the trench surface and a first conductive layer is then formed on the insulating layer to cover the liner oxide layer and fills the trench. A portion of the first conductive layer is removed, exposing a portion of the liner oxide layer. Next, the exposed liner oxide layer is removed to form a space which, along with the trench, is filled with a second conductive layer on the insulating layer. The detailed method may refer to U.S. Pat. No. 5,882,972, filed on Jul. 10, 1998. The buried bit line technology may also been used for other semiconductor device instead of DRAM. For example, U.S. Pat. No. 6,048,765 to Wu, entitled xe2x80x9cMethod of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gatexe2x80x9d. The method is disclosed for fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect. A further prior art may refer to U.S. Pat. No. 6,100,172, assigned to IBM, filed on Oct. 29, 1998.
As the feature of the circuits is shrinkage, the need for decreasing the electrical resistance associated with electrical connection or contact becomes more important than ever. The higher of the resistance, the slower is the circuits operating speed limited by the RC delay. The present invention will disclose a novel method of the buried bit line for semiconductor device such as DRAM, FLASH, SRAM and so on.
The object of the present invention is to form a conductive area in a trench by using an ion-implanted-sensitive resist. A method for manufacturing a conductive strip in a substrate having trench. An upper horizontal surface refers to the surface of the substrate. The trench includes vertical surfaces, and a lower horizontal surface. Wherein the upper surface includes a barrier formed thereon, the method comprises forming a doped dielectric layer along a surface of the barrier, the vertical surface and the lower horizontal surface. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface, thereby forming a conductive region and the barrier layer acting as a block to prevent the dopants from diffusing into the upper horizontal surface.
The doped dielectric layer includes phosphorus doped silicate glass or boron doped silicate glass. If the ion-implanted-sensitive resist includes silane-type resist, then the ions implanted by the vertical implantation includes oxygen. Alternatively, if the ion-implanted-sensitive resist includes polysilicon-type resist, then the ions implanted by the vertical implantation includes boron.